Chip design of an 8 MHz CMOS switched-capacitor low-pass filter for signal receiver applications

Author

Huang, Jhin-Fang ; Wen, Jiun-Yu ; Lai, Yan-Cheng ; Liu, Ron-Yi

Author_Institution

Dept. of Electron. Eng., Nat. Taiwan Univ. of Sci. & Technol., Taipei, Taiwan

Volume

9

fYear

2010

fDate

16-18 Oct. 2010

Firstpage

4037

Lastpage

4041

Abstract

In this paper, a fifth-order elliptical low-pass filter using switched-capacitor (SC) architecture is proposed. The filter has a pass-band of 8 MHz and clock frequency of 80 MHz. The proposed filter is realized by cascades of first-order and second-order biquad building blocks. In order to reach the largest possible input dynamic range and save chip area, the method of dynamic range scaling and minimum capacitor scaling is used. Measurement results show that the proposed SC low-pass filter achieves a pass-band frequency of 8.72 MHz. The chip area including pads is 0.895 mm² and the power dissipation is 44.2 mW at the supply voltage 1.8 V.

Keywords

CMOS integrated circuits; band-pass filters; biquadratic filters; elliptic filters; integrated circuit design; low-pass filters; radio receivers; switched capacitor filters; CMOS switched-capacitor low-pass filter; SC architecture; SC low-pass filter; chip design; dynamic range scaling method; fifth-order elliptical low-pass filter; frequency 8 MHz; frequency 8.72 MHz; frequency 80 MHz; minimum capacitor scaling; pass-band frequency; power 44.2 mW; power dissipation; second-order biquad filter; signal receiver; voltage 1.8 V; CMOS integrated circuits; Capacitors; Clocks; Frequency measurement; Low pass filters; RLC circuits; Switches; SC filter; biquad; dynamic range scaling; minimum capacitor scaling; switch sharing;

fLanguage

English

Publisher

ieee

Conference_Titel

Image and Signal Processing (CISP), 2010 3rd International Congress on

Conference_Location

Yantai

Print_ISBN

978-1-4244-6513-2

Type

conf

DOI

10.1109/CISP.2010.5648181

Filename

5648181