Title :
A Wiring-Efficient, High-Throughput Low Density Parity Check Decoder Design
Author :
Zarubica, Radivoje ; Wilson, Stephen G.
Author_Institution :
Dept. of Electr. & Comput. Eng., Virginia Univ., Charlottesville, VA
Abstract :
A high-throughput 1020-bit rate-1/2 low density parity check (LDPC) decoder design is proposed that matches the coding gain of current LDPC decoders. The decoder features wiring-efficient code design and an unwrapping technique that allows us to trade between size and the throughput of a decoder.
Keywords :
decoding; parity check codes; LDPC; low density parity check decoder design; unwrapping technique; wiring-efficient code design; Decoding; Error correction; Error correction codes; Hardware; Parity check codes; Satellite broadcasting; Sparse matrices; Turbo codes; Very large scale integration; Visualization;
Conference_Titel :
Information Sciences and Systems, 2006 40th Annual Conference on
Conference_Location :
Princeton, NJ
Print_ISBN :
1-4244-0349-9
Electronic_ISBN :
1-4244-0350-2
DOI :
10.1109/CISS.2006.286580
