Automatic synthesis of speed-independent circuits from signal transition graph specifications

We propose a verification method of the complete state coding property for signal transition graph specifications with single cycle signals. We also propose an optimized logic synthesis method for generating speed-independent circuits without the state graph representation. We use a circuit model for each non-input signal, which consists of a C-element and AND-gates. The resulting circuit is optimized by extracting the literals. We introduce semi-lock, full-lock, and associate-lock relations to generate circuits even though the lock graph by the full-lock relation is disconnected, Our method has polynomial complexity. We compare experimentally our method with other methods, and get better or equal results