Title :
Identifying redundant path delay faults in sequential circuits
Author :
Tekumalla, Ramesh ; Menon, P.R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
We define a class of faults called redundant path delay faults in sequential circuits, which do not effect circuit delay. A method of identifying redundant path delay faults in the next state logic implemented in a two-level sum-of-products form is presented. The method is extended to circuits with general multi-level realization of the next state logic. Experimental results for MCNC´91 benchmark circuits converted into a restricted factored form are also given
Keywords :
delays; fault diagnosis; logic testing; multivalued logic circuits; redundancy; sequential circuits; MCNC´91 benchmark circuits; multi-level realization; next state logic; redundant path delay faults; restricted factored form; sequential circuits; two-level sum-of-products form; Benchmark testing; Circuit faults; Circuit testing; Combinational circuits; Delay; Fault diagnosis; Logic circuits; Redundancy; Robustness; Sequential circuits;
Conference_Titel :
VLSI Design, 1996. Proceedings., Ninth International Conference on
Conference_Location :
Bangalore
Print_ISBN :
0-8186-7228-5
DOI :
10.1109/ICVD.1996.489643
