Identifying redundant path delay faults in sequential circuits

We define a class of faults called redundant path delay faults in sequential circuits, which do not effect circuit delay. A method of identifying redundant path delay faults in the next state logic implemented in a two-level sum-of-products form is presented. The method is extended to circuits with general multi-level realization of the next state logic. Experimental results for MCNC´91 benchmark circuits converted into a restricted factored form are also given