Statistical design of a multiplier using a low power square-law CMOS analog cell

Author

Tarim, Tuna B. ; Kuntman, H. Hakan ; Ismail, Mohammed

Author_Institution

Dept. of Electron. Eng., Istanbul Tech. Univ., Turkey

fYear

1998

fDate

30 Sep-3 Oct 1998

Firstpage

191

Lastpage

194

Abstract

The statistical design of a new multiplier using the square-law characteristics of MOS transistors in the saturation region is discussed in this paper. The multiplier is statistically robust and has a good yield. Initial simulation results of the circuit have been given and the offset current and nonlinearity of the multiplier have been statistically examined. Response Surface Methodology and Design of Experiments techniques were used as statistical VLSI design tools combined with the statistical MOS model. Device size optimization and yield enhancement have been demonstrated

Keywords

CMOS analogue integrated circuits; VLSI; analogue multipliers; circuit optimisation; design of experiments; integrated circuit design; low-power electronics; surface fitting; MOS transistors; design of experiments technique; device size optimization; low power analog cell; multiplier; nonlinearity; offset current; response surface methodology; saturation region; square-law CMOS analog cell; statistical MOS model; statistical VLSI design tools; statistical design; yield enhancement; Circuit simulation; Design engineering; Design methodology; Low voltage; MOSFETs; Power engineering and energy; Response surface methodology; Robustness; Threshold voltage; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design, 1998. Proceedings. XI Brazilian Symposium on

Conference_Location

Rio de Janeiro

Print_ISBN

0-8186-8704-5

Type

conf

DOI

10.1109/SBCCI.1998.715439

Filename

715439