Circuits for low power consumption in GaAs technology

In this paper we report the design of a new adder structure suitable for high speed, low power, digital applications. This adder was implemented using a new logic proposed recently, namely Pseudo-dynamic Latched Logic (PDDL), in MESFET technology using Vitesse H-GaAs III 0.6 μm technology. Static and pseudo-dynamic adders were studied in order to make comparisons in terms of delay and power dissipation. These circuits were chosen due to the fact that they have a strong influence on the performance of data and signal processors. HSPICE simulation indicates operation up to 833 MHz with a 1 V power supply. Considering the delay-power characteristics as a function of power supply, it was found that a good tradeoff is obtained when using a 1 V power supply. Power dissipation of 4.96 μW/MHz was obtained. Such extremely low power dissipation confirms that with this type of logic, high performance VLSI systems can be implemented