Debug Support for Hybrid SoCs

System-on-chip devices containing both conventional and reconfigurable circuits are increasing in popularity. However the on-chip debug support infrastructure required to aid systems development has not fully addressed the concept of such hybrid SoCs. This paper outlines the requirements for on-chip debug support with a focus on hard real-time systems. A generic approach to incorporate field programmable gate array based circuits into a system centric debug support methodology is introduced and a suitable interface defined. An assessment of the overhead introduced by adding debug support is made by synthesis of a configurable logic cell adapted to include debug support. The increase in overhead is found to be approximately 3.4 percent.