Low power VLSI circuit implementation using mixed static CMOS and domino logic with delay elements

The advent of dynamic CMOS logic, more precisely domino logic, made them widely used for the implementation of low power VLSI circuits. However, the main drawback of this logic is the non implementation of inverted logic. To implement the inverted logic, it is required to duplicate the logic circuit up to that part with inverted inputs. This obviously results the increase in area, delay as well as the power dissipation of the circuit. On the other hand, it is very simple to realize the circuit with both the inverted and non-inverted logic using static CMOS implementation. In this paper, this problem is addressed with the realization of the circuit which requires the implementation of inverted logic using mixed static and domino logic. To show the efficiency of the proposed model, a simple example like implementation of high fan-in NAND gate cascaded with AND gate is considered. With the comparison of all the three logics with a fixed fan-in of 7, 8 and 9 for both the gates, on an average 69.7% improvement is achieved in Power Delay Product (PDP), 11.4% improvement in area in terms of transistors using mixed logic implementation over static logic implementation and 68.64% improvement in PDP and 28.4% improvement in area over dynamic CMOS implementation when designed in 180nm technology.