Title :
Topography Simulation for Wafer-scale Structural Analysis
Author :
Lee, Jun-Gu ; Won, Taeyoung
Keywords :
Analytical models; Computational modeling; Dielectrics; Etching; Level set; Mesh generation; Parasitic capacitance; Read only memory; Surface topography; Testing;
Conference_Titel :
Semiconductor Device Research Symposium, 2005 International
Print_ISBN :
1-4244-0083-X
DOI :
10.1109/ISDRS.2005.1596146
