DocumentCode
3285548
Title
An efficient encoding scheme for ultra-fast flash ADC
Author
Choudbury, J. ; Cavanaugh, Charles ; Seetharaman, Guna
Author_Institution
Univ. of Louisiana, Lafayette, LA, USA
fYear
2003
fDate
15-17 Oct. 2003
Firstpage
38
Lastpage
39
Abstract
We propose an encoder design using the robust principle of programmable logic arrays (PLA). High-speed operation in the MHz-GHz range is the major goal of flash ADC design. High-speed ADC needs a fast comparator, a high-speed encoder and a fast sample-and-hold circuit. The paper discusses these three areas of high-speed ADC design; they each need equal careful attention.
Keywords
analogue-digital conversion; comparators (circuits); encoding; logic design; network synthesis; programmable logic arrays; ADC design; comparator; encoding scheme; programmable logic arrays; sample-and-hold circuit; ultra-fast flash ADC; CMOS technology; Delay; Encoding; Inverters; Logic design; Logic gates; MOS devices; MOSFETs; Programmable logic arrays; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Wireless Communication Technology, 2003. IEEE Topical Conference on
Print_ISBN
0-7803-8196-3
Type
conf
DOI
10.1109/WCT.2003.1321432
Filename
1321432
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