• DocumentCode
    3286003
  • Title

    Using Relocatable Bitstreams for Fault Tolerance

  • Author

    Montminy, David P. ; Baldwin, Rusty O. ; Williams, Paul D. ; Mullins, Barry E.

  • Author_Institution
    Air Force Inst. of Technol., Patterson
  • fYear
    2007
  • fDate
    5-8 Aug. 2007
  • Firstpage
    701
  • Lastpage
    708
  • Abstract
    The regular structure and addressing scheme for the Virtex-IIfamily of field programmable gate arrays (FPGAs) allows the relocation of partial bitstreams through direct bitstream manipulation. Our bitstream translation program relocates modules on an FPGA by changing the partial bitstream of the module. To take advantage of relocatable modules, three fault tolerant circuit designs are developed and tested. While operating through a fault, these designs provide support for efficient and transparent replacement of the faulty module with a relocated fault-free module. The architecture of the FPGA and static logic significantly constrain the placement of relocatable modules, especially when a microprocessor is placed on the FPGA.
  • Keywords
    fault tolerance; field programmable gate arrays; logic design; Virtex-II FPGA; bitstream translation program; direct bitstream manipulation; fault tolerant circuit design; field programmable gate array; static logic; Circuit faults; Circuit testing; Fault tolerance; Field programmable gate arrays; Integrated circuit interconnections; Logic devices; Military computing; Reconfigurable logic; Redundancy; Table lookup;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Adaptive Hardware and Systems, 2007. AHS 2007. Second NASA/ESA Conference on
  • Conference_Location
    Edinburgh
  • Print_ISBN
    978-0-7695-2866-3
  • Type

    conf

  • DOI
    10.1109/AHS.2007.108
  • Filename
    4291987