• DocumentCode
    3286138
  • Title

    A design model of gate-coupling NMOS ESD protection circuit

  • Author

    Yuan, Wang ; Song, Jia ; Zhongjian, Chen ; Ganggang, Zhang ; Lijiu, Ji

  • Author_Institution
    Inst. of Microelectron., Peking Univ., Beijing, China
  • Volume
    2
  • fYear
    2004
  • fDate
    18-21 Oct. 2004
  • Firstpage
    856
  • Abstract
    A design model is proposed to exactly simulate operating principles of gate-coupling NMOS (GCNMOS) ESD protection circuit under ESD stress. Using this model, adequate coupling capacitor Cn and coupling resistor Rn can be calculated to improve the efficiency of GCNMOS ESD protection circuit.
  • Keywords
    CMOS integrated circuits; capacitors; circuit simulation; electrostatic discharge; resistors; semiconductor device reliability; ESD stress; coupling capacitor; coupling resistor; gate-coupling NMOS ESD protection circuit; CMOS process; Capacitors; Coupling circuits; Electrostatic discharge; MOS devices; Protection; Resistors; Robustness; Stress; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
  • Print_ISBN
    0-7803-8511-X
  • Type

    conf

  • DOI
    10.1109/ICSICT.2004.1436642
  • Filename
    1436642
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3286138