Parameterized memory/processor optimizing FORTRAN compiler for parallel computers

A new approach to generating low-conflict parallel instructions for complex applications is introduced in this paper. This method is presented within the context of a FORTRAN compiler. An approximate simulator has been incorporated within a parallel-code/domain-decomposition loop within the compiler. The simulator estimates the performance of candidate instruction segments, and guides the selection of appropriate code transformations, heuristics, and data storage strategies. At present, many aspects of the target machine are parameterized, to permit investigations of a number of parallel-computer architectures. In this paper, the compiler is illustrated for a Navier-Stokes computer target node application