Design optimization of FPGA based viterbi decoder

In this paper, we propose a novel viterbi decoder in part parallel structure. The core part of the decoder-Add - Compare - Select Unit, is improved by means of pipeline. BMC (Branch Metric Computation) is improved through linear transform. TB (Trace Back) method is adopted for survivor path. The whole decoder has the advantages of speed and resource expense compared with traditional hybrid viterbi decoder. The decoder reduces combinational LUT (or register) consumption by 80% and memory blocks consumption by 50% compared with the viterbi IP core of Altera Corporation, while the former is similar to the latter in speed and BER performance. The channel rate of the decoder is up to 54Mbps on cyclone III.