VLSI design of fast DCTQ-IQIDCT processor for real time image compression

The Discrete Cosine Transform (DCT) is largely used for image and video compression in standards like JPEG and MPEG2. Its simplicity coupled with the fact that it can be computed faster than the Discrete Wavelet Transform (DWT) makes it an attractive option for image and video compression. Consequently a lot of research is in progress to determine novel architectures and algorithms for faster DCT computation having high throughput so that it can even be used for real time applications. For example, when transmitting and receiving videos, which have been compressed using MPEG2, one would like to receive the video, without any buffering delay. In other words, one requires such an architecture, which provides the DCTQ coeffecients at a consistent rate, with very low latency between two coeffecients. As such, a highly parallel and pipelined architecture employing 57 pipeline stages and using fast multipliers and adders is proposed in this work. The proposed DCT Processor is implemented in Spartan 3E FPGA.