Title :
On test generation for path delay faults in ASICs
Author_Institution :
Teradyne EDA, Santa Clara, CA, USA
Abstract :
Discusses automatic test pattern generation (ATPG) for path delay faults in application specific integrated circuits (ASICs). An ATPG that uses a modified FAN algorithm to generate tests for critical paths derived using static timing analysis is described. The test generation procedure is optimised through the use of path constrainment and the concept of mandatory assignments.<>
Keywords :
application specific integrated circuits; automatic testing; fault location; integrated circuit testing; logic testing; ASICs; ATPG; automatic test pattern generation; mandatory assignments; modified FAN algorithm; path constrainment; path delay faults; static timing analysis; test generation; Application specific integrated circuits; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Delay; Integrated circuit testing; Logic circuits; Timing; Very large scale integration;
Conference_Titel :
VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-7803-0623-6
DOI :
10.1109/VTEST.1992.232718
