DocumentCode :
3288392
Title :
Testability properties of acyclic structures and applications to partial scan design
Author :
Gupta, Rajesh ; Breuer, Melvin A.
Author_Institution :
IBM, Hopewell Junction, NY, USA
fYear :
1992
fDate :
7-9 April 1992
Firstpage :
49
Lastpage :
54
Abstract :
It is well known that acyclic sequential structures are considerably easier to test than cyclic sequential circuits. Hence some partial scan techniques attempt to simplify the test generation problem by ensuring that the portion of the circuit effectively under test is acyclic. In such designs the test time is dominated by the shifting of test patterns into and out of the scan path. The authors present a compacting technique that minimizes the number of distinct test patterns required to detect an arbitrary fault, thus minimizing the amount of data shifted in to detect the fault. The technique results in (1) a minimal compacted test schedule and (2) a condensed combinational test generation model, which can be used to generate and apply tests to the circuit in an efficient manner.<>
Keywords :
automatic testing; boundary scan testing; logic testing; sequential circuits; acyclic structures; combinational test generation model; compacted test schedule; compacting technique; partial scan design; sequential structures; test generation; test time; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Clocks; Contracts; Electrical fault detection; Kernel; Sequential analysis; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-7803-0623-6
Type :
conf
DOI :
10.1109/VTEST.1992.232723
Filename :
232723
Link To Document :
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