DocumentCode
3288419
Title
Design of low cost ROM based test generators
Author
Edirisooriya, Geetani ; Robinson, John P.
Author_Institution
Iowa Univ., Iowa City, IA, USA
fYear
1992
fDate
7-9 April 1992
Firstpage
61
Lastpage
66
Abstract
A data compression technique for ROM based built-in test generators of combinational circuits is described. Some of the test pattern bits are computed using the reduced data stored in the ROM combined with the address bits accessing the ROM. Some experimental results are presented for ISCAS benchmark circuits and random data.<>
Keywords
combinatorial circuits; data compression; logic testing; read-only storage; ISCAS benchmark circuits; ROM based test generators; built-in test generators; combinational circuits; data compression technique; random data; reduced data; test pattern bits; Automatic testing; Built-in self-test; Circuit testing; Cities and towns; Costs; Counting circuits; Multiplexing; Read only memory; Test pattern generators; Variable speed drives;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE
Conference_Location
Atlantic City, NJ, USA
Print_ISBN
0-7803-0623-6
Type
conf
DOI
10.1109/VTEST.1992.232725
Filename
232725
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