DocumentCode
3288522
Title
Hierarchical fault modeling for analog and mixed-signal circuits
Author
Nagi, Naveena ; Abraham, Jacob A.
Author_Institution
Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
fYear
1992
fDate
7-9 April 1992
Firstpage
96
Lastpage
101
Abstract
Presents a comprehensive approach, based on functional error characterization, for modeling faults in analog and mixed-signal circuits. A case study based on a CMOS and an nMOS operational amplifier is discussed, and a full listing of derived behavioral fault models is presented. These fault models are then mapped to the faulty behavior at the macro-circuit level.<>
Keywords
CMOS integrated circuits; MOS integrated circuits; fault location; linear integrated circuits; mixed analogue-digital integrated circuits; operational amplifiers; CMOS; behavioral fault models; faulty behavior; functional error characterization; macro-circuit level; mixed-signal circuits; nMOS operational amplifier; Analog circuits; Analog computers; Circuit faults; Circuit simulation; Circuit testing; Jacobian matrices; MOS devices; Operational amplifiers; Semiconductor device modeling; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE
Conference_Location
Atlantic City, NJ, USA
Print_ISBN
0-7803-0623-6
Type
conf
DOI
10.1109/VTEST.1992.232731
Filename
232731
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