On test generation for combinational circuits consisting of AND and EXOR gates

Author

Toida, S. ; Rao, N.S.V.

Author_Institution

Dept. of Comput. Sci., Old Dominion Univ., Norfolk, VA, USA

fYear

1992

fDate

7-9 April 1992

Firstpage

113

Lastpage

118

Abstract

Single output logic circuits composed of AND and EXOR gates are studied. It is shown that for two level single output logic circuits composed of AND and EXOR gates, tests that detect all detectable stuck-at faults can be generated in polynomial time. In this method no extra input variables nor extra circuits are required. This contrasts with the fact that for AND, OR circuits the test generation problem is not polynomial time solvable even for two level circuits. Since AND-EXOR circuits can represent any switching function, this suggests that these circuits might be easier to test than AND, OR circuits.<>

Keywords

combinatorial circuits; fault location; logic gates; logic testing; AND gates; EXOR gates; combinational circuits; detectable stuck-at faults; polynomial time; single output logic circuits; switching function; test generation; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Fault detection; Input variables; Logic circuits; Logic testing; Polynomials; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE

Conference_Location

Atlantic City, NJ, USA

Print_ISBN

0-7803-0623-6

Type

conf

DOI

10.1109/VTEST.1992.232734

Filename

232734