Title :
An investigation of circuit partitioning for parallel test generation
Author :
Bollinger, S. Wayne ; Midkiff, Scott F.
Author_Institution :
Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
Abstract :
Explores the feasibility of using circuit partitioning approach to reduce the run-time complexity of test generation via parallel processing. Characterization of the major phases of test generation is used to show how the inherent parallelism existing in test generation can be exploited during forward implication and backward justification. Upper bounds on the concurrency available in specific are empirically determined by simulating the behavior of a ´perfect´ conflict-free test generation algorithm that operates without backtracking. Results presented for a number of benchmark circuits indicate that the average available parallelism is fairly low, limiting the potential speedup of a circuit partitioning approach to test generation.<>
Keywords :
VLSI; combinatorial circuits; integrated circuit testing; integrated logic circuits; logic testing; backward justification; benchmark circuits; circuit partitioning; concurrency; conflict-free test generation algorithm; forward implication; parallel test generation; run-time complexity; speedup; Benchmark testing; Character generation; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Computational modeling; Concurrent computing; Parallel processing; Partitioning algorithms;
Conference_Titel :
VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE
Conference_Location :
Atlantic City, NJ, USA
Print_ISBN :
0-7803-0623-6
DOI :
10.1109/VTEST.1992.232735
