Design of reduced testing for VLSI circuits based on linear code theory

Author

Pimenta, Tales C. ; Mokari, M. Ebrahim

Author_Institution

Dept. of Electr. & Comput. Eng., Ohio Univ., Athens, OH, USA

fYear

1992

fDate

7-9 April 1992

Firstpage

131

Lastpage

136

Abstract

Pseudo-exhaustive testing can detect all stuck-at faults in combinational circuits. Although the testing time is reduced compared to exhaustive testing, it still remains long. In this paper, a design procedure which requires a minimum number of test vectors to detect all stuck-at faults is presented. The process is based on linear code theory, and different generator polynomials are used to design the LFSR. Fault simulation is used to evaluate the faults detected by each test vector generated consecutively by the LFSR. The LFSR resulting in a minimum number of test vectors is chosen for circuit implementation. The results show that this approach greatly reduces the test time of the actual circuit.<>

Keywords

VLSI; combinatorial circuits; integrated logic circuits; logic testing; LFSR; VLSI circuits; circuit implementation; combinational circuits; generator polynomials; linear code theory; linear feedback shift register; stuck-at faults; test vectors; testing time; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Electrical fault detection; Fault detection; Linear code; Logic testing; Test pattern generators; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE

Conference_Location

Atlantic City, NJ, USA

Print_ISBN

0-7803-0623-6

Type

conf

DOI

10.1109/VTEST.1992.232737

Filename

232737