Detection of multiple faults in CMOS circuits using a behavioral approach

Author

Shen, Y.-N. ; Lombardi, F.

Author_Institution

Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA

fYear

1992

fDate

7-9 April 1992

Firstpage

188

Lastpage

193

Abstract

Presents an approach for the detection of multiple stuck-open (SOP) and stuck-on (SON) faults in CMOS combinational logic circuits. It is proved that multiple SON and SOP faults do not mask each other. This is achieved using a behavioral analysis in which the maskable fault patterns are proved to be impossible. New testing approaches are proposed. Testing is implemented using a combination of two-pattern test sequences as well as universal test sets, as proposed in previous papers by different authors.<>

Keywords

CMOS integrated circuits; VLSI; combinatorial circuits; fault location; integrated logic circuits; CMOS circuits; SON faults; SOP faults; behavioral approach; combinational logic circuits; maskable fault patterns; multiple faults; stuck-on faults; stuck-open faults; two-pattern test sequences; universal test sets; CMOS logic circuits; CMOS technology; Circuit analysis; Circuit faults; Circuit testing; Combinational circuits; Computer science; Electrical fault detection; Fault detection; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE

Conference_Location

Atlantic City, NJ, USA

Print_ISBN

0-7803-0623-6

Type

conf

DOI

10.1109/VTEST.1992.232747

Filename

232747