• DocumentCode
    3288836
  • Title

    Honeywell radiation hardened 32-bit processor central processing unit, floating point processor, and cache memory dose rate and single event effects test results

  • Author

    Brown, Gary R. ; Hoffmann, Lee F. ; Leavy, Scott C. ; Mogensen, Jeffrey A. ; Brichacek, Julie

  • Author_Institution
    Honeywell Inc., Clearwater, FL, USA
  • fYear
    1997
  • fDate
    35635
  • Firstpage
    110
  • Lastpage
    115
  • Abstract
    We will present single event effects and dose rate test results for the Honeywell Radiation Hardened 32-Bit Processor Central Processing Unit, Floating Point Processor and Cache Memory. These three chip types comprise the processor core for a 32-bit radiation-hardened, fault-tolerant processor
  • Keywords
    cache storage; fault tolerant computing; floating point arithmetic; microprocessor chips; radiation hardening (electronics); 32 bit; Honeywell processor; RH32 chip; cache memory; central processing unit; dose rate; fault-tolerant processor; floating point processor; radiation hardening; single event effects; Cache memory; Central Processing Unit; Circuit faults; Fault tolerance; Flip-flops; Laboratories; Orbits; Radiation hardening; Single event upset; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Radiation Effects Data Workshop, 1997 IEEE
  • Conference_Location
    Snowmass Village, CO
  • Print_ISBN
    0-7803-4061-2
  • Type

    conf

  • DOI
    10.1109/REDW.1997.629808
  • Filename
    629808
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3288836