DocumentCode
3288873
Title
Die attach quality control of 3D stacked dies
Author
Rencz, M. ; Székely, V. ; Courtois, B. ; Zhang, L. ; Howard, N. ; Nguyen, L.
Author_Institution
MicReD Ltd., Budapest, Hungary
fYear
2004
fDate
July 14-16, 2004
Firstpage
78
Lastpage
84
Abstract
In this paper, we present a methodology that can be used to determine the die attach failures of packaged stacked die structures. After presenting the methodology simulation experiments show the applicability for stacked die packages. The accuracy issues are discussed by evaluating the first measured results. The results of blind tests measurements are also presented. With the evaluation of these measurements we demonstrate that the methodology is in fact applicable to find the location of the integrity problems also within packages containing stack dies.
Keywords
chip scale packaging; failure analysis; integrated circuit reliability; microassembling; 3D stacked dies; accuracy issues; blind tests measurements; die attach failures; die attach quality control; packaged stacked die structures; Capacitance; Electrical resistance measurement; Electron devices; Laboratories; Microassembly; Quality control; Semiconductor device packaging; Semiconductor device testing; Temperature; Thermal resistance;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Manufacturing Technology Symposium, 2004. IEEE/CPMT/SEMI 29th International
ISSN
1089-8190
Print_ISBN
0-7803-8582-9
Type
conf
DOI
10.1109/IEMT.2004.1321636
Filename
1321636
Link To Document