• DocumentCode
    3288887
  • Title

    Advanced wire bond looping technology for emerging packages

  • Author

    Brunner, Jon ; Qin, Ivy Wei ; Chylak, Bob

  • Author_Institution
    Kulicke & Soffa, Willow Grove, PA, USA
  • fYear
    2004
  • fDate
    July 14-16, 2004
  • Firstpage
    85
  • Lastpage
    90
  • Abstract
    Advanced packaging requirements for emerging semiconductor devices continue to present new challenges to the wire bond process. As an alternative to reducing pad pitch on high I/O applications, multi-tiered pad arrangements are typically found in production today with two, three or even four rows of bond pads. The growth of stacked die packages, and its requirement for a low profile, also challenges the wire bonding process. This paper examines looping advancements in today´s wire bonders that have been developed to meet the unique challenges associated with multi-tied and stacked die applications. Featured looping profiles include both forward and reversed bonding and the newly developed folded forward and lateral looping profiles. The advantages and trade-offs for each profile are outlined in the article. Capabilities including minimal loop height, productivity, fine pitch capability, and wire sweep resistance are compared for the different types of trajectories. In addition to looping trajectories, copper wire advantages are discussed in the context of a 60μm quad-tier demonstration. Driven by the complexity of multi-layered looping applications, a new K&S test device has been designed and produced in collaboration with key customers. The die will be used for developing multi-tiered approaches to ultra-high density packaging with wire bond interconnects.
  • Keywords
    copper; fine-pitch technology; integrated circuit bonding; integrated circuit interconnections; lead bonding; semiconductor device packaging; I-O applications; K&S test device; bond pads; copper wire; fine pitch capability; forward bonding; loop height; looping profiles; looping trajectories; multilayered looping applications; multitiered pad arrangements; pad pitch reduction; reversed bonding; semiconductor devices; stacked die packages; wire bond interconnects; wire bond looping technology; wire bond process; wire sweep resistance; Bonding processes; Consumer electronics; Electronics packaging; Milling machines; Production; Semiconductor device packaging; Stacking; Substrates; Wafer bonding; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Manufacturing Technology Symposium, 2004. IEEE/CPMT/SEMI 29th International
  • ISSN
    1089-8190
  • Print_ISBN
    0-7803-8582-9
  • Type

    conf

  • DOI
    10.1109/IEMT.2004.1321637
  • Filename
    1321637