On-chip current sensing circuit for CMOS VLSI

Author

Tung-Li Shen ; Daly, J.C. ; Jien-Chung Lo

Author_Institution

United Microelectronics Corp., HsingChu, Taiwan

fYear

1992

fDate

7-9 April 1992

Firstpage

309

Lastpage

314

Abstract

CMOS is a popular technology today for very large scale integrated (VLSI) circuits. But, conventional functional testing cannot guarantee the detection of some defects. Built-in current testing has been suggested to enhance the defect coverage. In this paper, the authors present a high-speed built-in current sensing (BICS) circuit design. An experimental CMOS VLSI chip containing BICS is described. The power bus current of an 8*8 parallel multiplier is monitored. This BICS detects all implanted short circuit defects and some open circuit defects at a clock speed of 30 MHz (limited by the test set up). SPICE3 simulations indicate a defect detection time of 2 ns.<>

Keywords

CMOS integrated circuits; VLSI; built-in self test; integrated circuit testing; integrated logic circuits; logic testing; 2 ns; 30 MHz; CMOS VLSI; SPICE3 simulations; built-in current sensing; high-speed circuit; implanted short circuit defects; onchip current sensing circuit; open circuit defects; parallel multiplier; power bus current; very large scale integrated; CMOS logic circuits; Circuit faults; Circuit simulation; Circuit testing; Fabrication; Microelectronics; System testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE

Conference_Location

Atlantic City, NJ, USA

Print_ISBN

0-7803-0623-6

Type

conf

DOI

10.1109/VTEST.1992.232771

Filename

232771