The Implementation of Single-Phase Power-Gating Adiabatic Circuits Using Improved CAL Circuits

This paper focuses on the full-custom layout implementation of the single-phase power-gating adiabatic circuits. A transmission gate is used as the power-gating switch, and the power-gated adiabatic logic block uses the CAL (clocked adiabatic logic) circuits. A power-gating 8-bit full adder based on improved CAL circuits is verified. For a comparison, an 8-bit full adder based on improved CAL circuits without power-gating has also been drawn. All circuits are implemented with TSMC 0.18 um process. The energy and functional simulations have been performed using the net-list extracted from their layouts. The results show the improved CAL 8-bit full adder with the power-gating scheme can work very well, and it attains more than 36.2% power reductions than the 8-bit full adder without power-gating at 100 MHz when active is 0.2.