• DocumentCode
    3289512
  • Title

    How can design for manufacturing improve mask cost and yield?

  • Author

    Cote, Michel ; Hurat, Philippe ; Rieger, Mike ; Miloslavsky, Alexander ; Goinard, Denis

  • Author_Institution
    Synopsis Inc., Mountain View, CA, USA
  • fYear
    2004
  • fDate
    July 14-16, 2004
  • Firstpage
    273
  • Lastpage
    276
  • Abstract
    The relentless pursuit of Moore´s Law is pushing lithographical equipment to its limits. Extensive use of resolution enhancement technologies (RET) during mask synthesis has allowed the industry to meet demand for density and performance at the 0.13um node and below. RET has been used to sustain the traditional model of printing edges as close as possible to the corresponding edges in the design layout. As technology moves to sub-100nm processes, this model is proving to be both challenging and expensive to sustain. Pushing the RET tools to do an aggressive match between layout geometries and the printed pattern results in a large increase in mask cost. Even if this optimization is successful, the resulting pattern may not provide the highest possible yield. By providing design intent information along with the design layout, the mask synthesis (MS) flow is able to optimize the printed pattern for both improved yield and mask cost reduction (Rieger, et al., 2002). This paper describes the challenges faced by the mask synthesis flow and how it can be improved using design intent, which is generated as part of the design flow. It describes specific details on the content of design intent. It also presents some experimental results on the benefits of this flow in mask shot count and sliver count reduction.
  • Keywords
    design for manufacture; integrated circuit yield; masks; optimised production technology; semiconductor device manufacture; Moores Law; design intent information; design layout; edge printing; layout geometry; lithographical equipment; manufacturing design; mask cost reduction; mask shot count reduction; mask sliver count reduction; mask synthesis flow; printed pattern; process optimization; resolution enhancement technology; yield improvement; Cost function; Design optimization; Electronics industry; Geometry; Manufacturing; Moore´s Law; Pattern matching; Printing; Semiconductor device manufacture; Silicon;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Manufacturing Technology Symposium, 2004. IEEE/CPMT/SEMI 29th International
  • ISSN
    1089-8190
  • Print_ISBN
    0-7803-8582-9
  • Type

    conf

  • DOI
    10.1109/IEMT.2004.1321675
  • Filename
    1321675