Variable Block Size Architecture for Loops

This paper proposes a cache reconfiguration method to find the optimal block size for various variables accessed in loops. The method involves analyzing the temporal and spatial locality of the variables based on the data dependences of the variables in a loop obtained from their reference and offset matrices, formulating an optimization problem with the objective to minimize the average memory access time and solving it for the optimal block size for each of the variables for any given cache size. The paper proposes a cache architecture that places the variables in the cache with their respective block sizes and accesses them to achieve minimum average memory access time. Simulations support the theoretical results. The proposed model performs better than prefetching for chosen example.