DocumentCode
3290353
Title
Fast evaluation of protocol processor architectures for IPv6 routing
Author
Lilius, Johan ; Truscan, Dragos ; Virtanen, Seppo
Author_Institution
Embedded Syst. Lab., Turku Centre for Comput. Sci., Finland
fYear
2003
fDate
2003
Firstpage
158
Abstract
In this paper we present a design case study in configuring our protocol processor architecture to meet the performance requirements of IPv6 routing at gigabit speeds. Our methodology makes it possible to make fast reliable analyses of the problem on a high level and to find its key bottlenecks and design constraints. Based on the analyses we suggest architectural configurations for the target application. The best configurations can then be further analyzed in more detailed system-level simulations and physical estimations.
Keywords
application specific integrated circuits; hardware-software codesign; microprocessor chips; transport protocols; IPv6 routing; architectural configurations; design constraints; key bottlenecks; performance requirements; physical estimations; protocol processor architectures; system-level simulations; Clocks; Computer architecture; Computer science; Data buses; Embedded system; Hardware; Multiprocessor interconnection networks; Network synthesis; Routing protocols; Transport protocols;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe Conference and Exhibition, 2003
ISSN
1530-1591
Print_ISBN
0-7695-1870-2
Type
conf
DOI
10.1109/DATE.2003.1186688
Filename
1186688
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