Title :
Understanding Scalability and Performance Requirements of I/O-Intensive Applications on Future Multicore Servers
Author :
Akram, Shoaib ; Marazakis, Manolis ; Bilas, Angelos
Author_Institution :
Inst. of Comput. Sci. (ICS), Found. for Res. & Technol. - Hellas (FORTH), Heraklion, Greece
Abstract :
Today, there is increased interest in understanding the impact of data-centric applications on compute and storage infrastructures as datasets are projected to grow dramatically. In this paper, we examine the storage I/O behavior of twelve data-centric applications as the number of cores per server grows. We configure these applications with realistic datasets and examine configuration points where they perform significant amount of I/O. We propose using cycles per I/O (cpio) as a metric for abstracting many I/O subsystem configuration details. We analyze specific architectural issues pertaining to data-centric applications including the usefulness of hyperthreading, sensitivity to memory bandwidth, and the potential impact of disruptive storage technologies. Our results show that today´s data-centric applications are not able to scale with the number of cores: moving from one to eight cores, results in 0% to 400% more cycles per I/O operation. These applications can achieve much of their performance with only 50% of the memory bandwidth available on modern processors. Hyper-threading is extremely effective for these applications and, on average, applications suffer only a 15% reduction in performance when hyper-threading is used instead of full cores. Further, DRAM-type persistent memory has the potential to solve scalability bottlenecks by reducing or eliminating idle and I/O completion periods and improving server utilization. We use a detailed methodology to project that in the year 2020, at 4096 processors, servers will require between 250-500 GB/s under optimistic scaling assumptions. We show that if the current trend in application scalability is not reversed, we will need about 2.5M servers that will consume 10 BKWh of energy to do a single pass over the projected 35 Zeta Bytes of data in 2020.
Keywords :
DRAM chips; input-output programs; multi-threading; multiprocessing systems; parallel architectures; performance evaluation; storage allocation; DRAM-type persistent memory; I/O completion periods; I/O subsystem configuration details; I/O-intensive applications; cpio; cycles-per I/O; data-centric applications; disruptive storage technologies; hyper-threading; idle elimination; idle reduction; memory bandwidth; multicore servers; performance requirements; scalability requirements; server utilization improvement; Bandwidth; Databases; Hardware; Market research; Measurement; Scalability; Servers;
Conference_Titel :
Modeling, Analysis & Simulation of Computer and Telecommunication Systems (MASCOTS), 2012 IEEE 20th International Symposium on
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4673-2453-3
DOI :
10.1109/MASCOTS.2012.29