Effect of body-charge on fully- and partially-depleted SOI MOSFET design

Author

Sherony, M.J. ; Wei, A. ; Antoniadis, D.A.

Author_Institution

Microsystems Technol. Lab., MIT, Cambridge, MA, USA

fYear

1996

fDate

8-11 Dec. 1996

Firstpage

125

Lastpage

128

Abstract

This work presents a new method for assessing the effect of floating-body charge on a fully- and partially depleted SOI device design space. Floating-body effects are incorporated into the device design criteria, V/sub T/ and I/sub OFF/ via transient-based evaluation of device performance using calibrated 2-D device simulation. Using this methodology, the worst-case shifts in V/sub T/ and I/sub OFF/ due to hysteretic floating-body charge are quantified for L/sub eff/-0.2 /spl mu/m and 0.1 /spl mu/m design spaces. The effect of reducing effective bulk lifetime in widening the 0.1 /spl mu/m design space is demonstrated.

Keywords

MOSFET; carrier lifetime; semiconductor device models; silicon-on-insulator; 0.1 micron; 0.2 micron; calibrated 2D device simulation; device design criteria; effective bulk lifetime; fully-depleted SOI MOSFET; hysteretic floating-body charge; partially-depleted SOI MOSFET; transient-based evaluation; worst-case shifts; Electrostatics; Hysteresis; Impact ionization; Laboratories; MOS devices; MOSFET circuits; Nanoscale devices; Space charge; Space technology; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1996. IEDM '96., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-3393-4

Type

conf

DOI

10.1109/IEDM.1996.553137

Filename

553137