An 11-Gb/s Receiver With a Dynamic Linear Equalizer in a 22-nm CMOS

A receiver circuit employing a dynamic linear equalization technique is presented. The new circuit method removes the traditional continuous-time linear equalizer (CTLE) and builds equalization into strong-arm latches (SALs). Fabricated in a 22-nm CMOS technology, the receiver´s performance is experimentally verified at 11 Gb/s with better than bit error rate 10^-12 at 0.17 mW/Gb/s power efficiency, which advances the state of the art. The power efficiency is 55% better than the CTLE alternative on the same silicon. Analysis and simulation methods for the dynamic linear equalization and other architectural details are also presented.