Title :
ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology
Author :
Stensgaard, Mikkel B. ; Sparso, J.
Author_Institution :
Tech. Univ. of Denmark (DTU), Lyngby
Abstract :
This paper presents a network-on-chip (NoC) architecture that enables the network topology to be reconfigured. The architecture thus enables a generalized System.-on-Chip (SoC) platform in which the topology can be customized for the application that is currently running on the chip, including long links and direct links between IP-blocks. The configurability is inserted as a layer between routers and links, and the architecture can therefore be used in combination with existing NoC routers, making it a general architecture. The topology is configured using energy-efficient topology switches based on physical circuit-switching as found in FPGAs. The paper presents the ReNoC (Reconfigurable NoC) architecture and evaluates its potential. The evaluation design shows a 56% decrease in power consumption compared to a static 2D mesh topology.
Keywords :
field programmable gate arrays; logic design; network topology; network-on-chip; FPGA; IP-blocks; NoC routers; energy-efficient topology switches; network-on-chip architecture; physical circuit-switching; reconfigurable topology; system-on-chip; CMOS technology; Circuit topology; Energy consumption; Energy efficiency; Field programmable gate arrays; Network topology; Network-on-a-chip; Switches; Switching circuits; System-on-a-chip; Application-specific; Communication; Network-on-Chip; Reconfigurable; System-on-Chip;
Conference_Titel :
Networks-on-Chip, 2008. NoCS 2008. Second ACM/IEEE International Symposium on
Conference_Location :
Newcastle upon Tyne
Print_ISBN :
0-7695-3098-2
DOI :
10.1109/NOCS.2008.4492725
