DocumentCode
329104
Title
Fault-tolerant neural architectures: a general approach to concurrent diagnosis based on signature analysis
Author
Demidenko, Serge ; Piuri, Vincenzo ; Sami, Mariagiovanna ; Stefanelli, Renato
Author_Institution
Inst. of Eng. Cybern., Acad. of Sci., Minsk, Byelorussia
Volume
2
fYear
1993
fDate
25-29 Oct. 1993
Firstpage
1917
Abstract
Diagnosis is a basic issue of any fault-tolerance policy. Fault localization within the neural architecture is necessary to provide information for hardware reconfiguration in order to achieve system survival (possibly with reduced computational capabilities). In this paper, a concurrent approach and distributed schemes for signature compression are proposed and evaluated.
Keywords
fault diagnosis; fault tolerant computing; logic testing; neural net architecture; neural nets; parallel architectures; concurrent diagnosis; fault diagnosis; fault localization; fault-tolerant neural architectures; signature analysis; signature compression; Circuit faults; Circuit testing; Computer architecture; Fault detection; Fault diagnosis; Fault tolerance; Hardware; Image coding; Neurons; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Neural Networks, 1993. IJCNN '93-Nagoya. Proceedings of 1993 International Joint Conference on
Print_ISBN
0-7803-1421-2
Type
conf
DOI
10.1109/IJCNN.1993.717030
Filename
717030
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