DocumentCode
329116
Title
A chip design of generalized winner-take-all circuit
Author
Ando, Tsuyoshi ; Koi, Katsuhiko ; Aibara, Reiji ; Ae, Tadashi
Author_Institution
Fac. of Eng., Hiroshima Univ., Japan
Volume
2
fYear
1993
fDate
25-29 Oct. 1993
Firstpage
1971
Abstract
Designs a chip of generalized winner-take-all circuit format for semantic applications such as databases. The realization using the optical interconnection is also considered.
Keywords
VLSI; learning (artificial intelligence); neural chips; self-organising feature maps; vector quantisation; databases; generalized winner-take-all circuit; optical interconnection; semantic applications; Algorithm design and analysis; Binary trees; Chip scale packaging; Circuits; Data engineering; Databases; Decoding; Design engineering; Detectors; Optical interconnections;
fLanguage
English
Publisher
ieee
Conference_Titel
Neural Networks, 1993. IJCNN '93-Nagoya. Proceedings of 1993 International Joint Conference on
Print_ISBN
0-7803-1421-2
Type
conf
DOI
10.1109/IJCNN.1993.717043
Filename
717043
Link To Document