Title :
Digital CMOS VLSI processor design for the implementation of neural networks using linear wavefront architecture
Author :
Conti, M. ; Orcioni, S. ; Piazza, F. ; Turchetti, C.
Author_Institution :
Dipartimento di Elettronica, Ancona Univ., Italy
Abstract :
This paper presents a digital VLSI implementation of a neural network model using a linear array of processing elements. The pipelined architecture we suggest along with a proper processor design result in a modular and reconfigurable parallel structure capable of high throughput.
Keywords :
CMOS digital integrated circuits; VLSI; integrated circuit design; microprocessor chips; multilayer perceptrons; neural chips; neural net architecture; parallel architectures; pipeline processing; reconfigurable architectures; digital CMOS VLSI processor design; high throughput; linear processing element array; linear wavefront architecture; modular reconfigurable parallel structure; multilayer perceptron network; neural network model implementation; pipelined architecture; processor design; Artificial neural networks; CMOS process; Clocks; Computer architecture; Hardware; Neural networks; Neurons; Process design; Silicon; Very large scale integration;
Conference_Titel :
Neural Networks, 1993. IJCNN '93-Nagoya. Proceedings of 1993 International Joint Conference on
Print_ISBN :
0-7803-1421-2
DOI :
10.1109/IJCNN.1993.717044
