Title :
A 2.5 GHz CMOS dual-modulus prescaler for RF frequency synthesizer
Author :
Yang, Wen-Rong ; Jia-Lin Lao ; Ran, Fen ; Wang, Jian
Author_Institution :
Center for Microelectron. Res. Dev., Shanghai Univ., China
Abstract :
A high-speed dual-modulus divide-by-32/33 prescaler has been developed in a 0.25 μm CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed tradeoff. The proposed prescaler can operate at high frequency with a low-power consumption. Based on the 2.5V 0.25 μm CMOS model, simulation results indicate that the maximum input frequency of the prescaler is up to 3.2 GHz. Running at a power supply of 2.5V, the circuit consumes only 4.6 mA at input frequency of 2.5 GHz.
Keywords :
CMOS logic circuits; frequency synthesizers; logic design; low-power electronics; prescalers; 0.25 micron; 2.5 GHz; 2.5 V; 4.6 mA; CMOS dual-modulus prescaler; RF frequency synthesizer; divide-by-32/33 prescaler; power speed tradeoff; source coupled logic structure; switching noise reduction; CMOS logic circuits; CMOS technology; Counting circuits; Frequency synthesizers; Gallium arsenide; Noise reduction; Phase locked loops; RNA; Radio frequency; Voltage-controlled oscillators;
Conference_Titel :
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN :
0-7803-8511-X
DOI :
10.1109/ICSICT.2004.1436910
