DocumentCode :
3291220
Title :
Frequency Affinity: Analyzing and Maximizing Power Efficiency in Multi-core Systems
Author :
Jia, Gangyong ; Li, Xi ; Wang, Chao ; Zhou, Xuehai ; Zhu, Zongwei
Author_Institution :
Dept. of Comput. Sci. & Technol., Univ. of Sci. & Technol. of China (USTC), Hefei, China
fYear :
2012
fDate :
7-9 Aug. 2012
Firstpage :
495
Lastpage :
497
Abstract :
Performance optimization and energy efficiency are the major challenges in multi-core system design. Of the state-of-the-art approaches, cache affinity aware scheduling and techniques based on dynamic voltage frequency scaling (DVFS) are widely applied to improve performance and save energy consumptions respectively. In modern operating systems, schedulers exploit high cache affinity by allocating a process on a recently used processor whenever possible. When a process runs on a high-affinity processor it will find most of its states already in the cache and will thus achieve more efficiency. However, most state-of-the-art DVFS techniques do not concentrate on the cost analysis for DVFS mechanism. In this paper, we firstly propose frequency affinity which retains the voltage frequency as long as possible to avoid frequently switching, and then present a frequency affinity aware scheduling (FAS) to maximize power efficiency for multi-core systems. Experimental results demonstrate our frequency affinity aware scheduling algorithms are much more power efficient than single-ISA heterogeneous multi-core processors.
Keywords :
cache storage; energy conservation; energy consumption; multiprocessing systems; power aware computing; processor scheduling; DVFS mechanism; FAS; cache affinity aware scheduling; cost analysis; dynamic voltage frequency scaling; energy consumption; energy efficiency; frequency affinity aware scheduling algorithm; high-affinity processor; multicore system design; performance optimization; power efficiency; single-ISA heterogeneous multicore processor; Instruction sets; Multicore processing; Optimization; Processor scheduling; Scheduling; Switches; Time frequency analysis; DVFS; cache affinity; frequency affinity; power efficiency; scheduling; single-ISA heterogeneous multi-core;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Modeling, Analysis & Simulation of Computer and Telecommunication Systems (MASCOTS), 2012 IEEE 20th International Symposium on
Conference_Location :
Washington, DC
ISSN :
1526-7539
Print_ISBN :
978-1-4673-2453-3
Type :
conf
DOI :
10.1109/MASCOTS.2012.63
Filename :
6298212
Link To Document :
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