Title :
Implementation of Wave-Pipelined Interconnects in FPGAs
Author :
Mak, Terrence ; Alessandro, Crescenzo D. ; Sedcole, Pete ; Cheung, Peter Y K ; Yakovlev, Alex ; Luk, Wayne
Author_Institution :
Imperial Coll. London, London
Abstract :
Global interconnection and communication at high clock frequencies are becoming more problematic in FPGA. In this paper, we address this problem by presenting an interconnect wave-pipelining strategy, which utilizes the existing programmable interconnects fabrics to provide high-throughput communication in FPGA. Two design approaches for interconnect wave-pipelining, using simple clock phase shifting and asynchronous phase encoding, are presented in this paper. Experimental results from a Xilinx Virtex-5 FPGA device are also presented.
Keywords :
field programmable gate arrays; phase coding; phase shifters; pipeline processing; FPGA; Xilinx Virtex-5; asynchronous phase encoding; clock phase shifting; global communication; global interconnection; wave-pipelined interconnects; Clocks; Delay; Encoding; Field programmable gate arrays; Frequency; Integrated circuit interconnections; Robustness; Shift registers; Throughput; Wire;
Conference_Titel :
Networks-on-Chip, 2008. NoCS 2008. Second ACM/IEEE International Symposium on
Conference_Location :
Newcastle upon Tyne
Print_ISBN :
0-7695-3098-2
DOI :
10.1109/NOCS.2008.4492743
