A Design and Implementation of Decimal Floating-point Multiplication Unit Based on SOPC

Processor design is a widely studied topic in computer system architecture design. How to improve computer performance is an important part of the computer overall design. In general processors, multiplication components play a decisive role in processor´s performance. An important and frequent operation in decimal computations is multiplication. However, due to the inherent inefficiency of decimal arithmetic implementations in binary logic, practically all the proposed decimal multipliers are sequential units. Binary computing couldn´t be avoided of conversion efficiency lowly and loss of accuracy. In this paper direct expanding the decimal computing applications and binary can´t meet the needs of decimal operations, according to this new standard IEEE-754r, use SOPC technology design and implement a new architecture based on the decimal floating-point multiplication unit. This design takes advantage of flexibility and low-power of SOPC, the independence of IP core and so on; it is packaged as an independent IP core. This decimal floating-point multiplication unit is broadly applications in the general processors, portable devices, and mass data processing and so on. It uses Signed-Digit radix-4 algorithm and new BCD coding techniques for the decomposition of decimal floating-point computing. and compared with the common single-precision binary floating-point unit, it was wider computing, higher accuracy, faster computing speed and wider application. The main contributions of this paper include: (1) Customized a 32/64 bit fully functional decimal floating point multiplication IP core; (2) Improved partial products based on the BCD-8421 and revised parts of the circuit; (3) According to the customized component operational requirements, defined a way of data bus, caused decimal floating point multiplication unit is good access SOPC system bus. This unit can be well used to processors, which support the standard of decimal floating-point operations, to improve pr- cessor performance. This model is verified by synthesis to Altera´s low cost Cyclone II FPGA.