Improving code density using compression techniques

Author

Lefurgy, Charles ; Bird, Peter ; Chen, I-Cheng ; Mudge, Trevor

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA

fYear

1997

fDate

1-3 Dec 1997

Firstpage

194

Lastpage

203

Abstract

Proposes a method for compressing programs in embedded processors where the instruction memory size dominates the cost. A post-compilation analyzer examines a program and replaces common sequences of instructions with a single instruction codeword. A microprocessor executes the compressed instruction sequences by fetching codewords from the instruction memory, expanding them back to the original sequence of instructions in the decode stage, and issuing them to the execution stages. We apply our technique to the PowerPC, ARM and i386 instruction sets and achieve an average size reduction of 39%, 34% and 26%, respectively, for SPEC CINT95 programs

Keywords

computer architecture; decoding; instruction sets; source coding; ARM instruction set; PowerPC instruction set; SPEC CINT95 programs; code density; common instruction sequences; compressed instruction sequences; cost; decoding stage; embedded processors; execution stages; i386 instruction set; instruction codeword fetching; instruction memory size; microprocessor; post-compilation analyser; program compression techniques; size reduction; Bandwidth; Birds; Circuits; Costs; Decoding; Embedded system; Encoding; Instruction sets; Microprocessors; Statistics;

fLanguage

English

Publisher

ieee

Conference_Titel

Microarchitecture, 1997. Proceedings., Thirtieth Annual IEEE/ACM International Symposium on

Conference_Location

Research Triangle Park, NC

ISSN

1072-4451

Print_ISBN

0-8186-7977-8

Type

conf

DOI

10.1109/MICRO.1997.645810

Filename

645810