A 5 MHz silicon CMOS hierarchical boost DC-DC converter design using macromodels for a 1U process

This work presents an innovative design of a high frequency and potentially highly efficient boost DC-DC converter with an input voltage of 2.7-3.3 V and with a programmable output voltage of 4-9 V. Current sourcing capability is between 40 mA-360 mA. A low power boost DC-DC converter designed in CMOS which partially uses circuit macromodels-designed and tested using Cadence tools-for an all CMOS silicon process illustrates this design. The key features of this design are very high switching frequency, reconfigurability, silicon all CMOS implementation, and mixed signal simulation capability. The boost converter has a simulation switching frequency of 5 MHz, an average efficiency of 50% and an output ripple voltage of about 30 mV.