A scalable architecture of associative processors employing nano functional devices

A methodology for building a low-power high-capacity associative processor system employing nano functional devices has been proposed. The study is a demonstration of how to use nano-scale devices in building practical applications, particularly in building associative processors. Characteristics of such devices are utilized for similarity evaluation and emulated by a simple NMOS circuitry. The concept has been verified by experimental results obtained from the real working proof-of-concept chip fabricated in a 0.18-mum CMOS technology.