• DocumentCode
    3292810
  • Title

    NBTI tolerant 4T double-gate SRAM design

  • Author

    Ebrahimi, Behzad ; Afzali-Kusha, Ali

  • Author_Institution
    Sch. of Electr. & Comput. Eng., Univ. of Tehran, Tehran
  • fYear
    2009
  • fDate
    18-20 March 2009
  • Firstpage
    221
  • Lastpage
    224
  • Abstract
    In this paper, we propose 4T FinFET SRAM cells which are robust against NBTI effect. The cells, which only use NMOS or PMOS transistors in their structures, are called 4TLLFBNO and 4TDLFBPO, respectively. The simulation results at iso-area design reveal that 4TLLFBNO has the highest read current and 4TDLFBPO has the least power consumption among different cells. Both cells are expected to be robust for at least 3 years against the NBTI degradation considering the read and hold SNMs. Read current is also not degraded considerably in comparison with previous cells. The cells have good write SNM and write time and outperform the pervious cells in terms of the maximum number of cells per column without degrading by NBTI effect.
  • Keywords
    MOSFET; SRAM chips; semiconductor device reliability; thermal stability; 4T FinFET SRAM cell; NBTI tolerance; NMOS transistors; PMOS transistors; negative-bias temperature instability; power consumption; reliability aware design; CMOS technology; Degradation; FinFETs; Logic; MOS devices; MOSFETs; Niobium compounds; Random access memory; Robustness; Titanium compounds; 4T SRAM; Double-gate; NBTI; Reliability aware design;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Ultimate Integration of Silicon, 2009. ULIS 2009. 10th International Conference on
  • Conference_Location
    Aachen
  • Print_ISBN
    978-1-4244-3704-7
  • Type

    conf

  • DOI
    10.1109/ULIS.2009.4897576
  • Filename
    4897576