Simulation assessment of process options for advanced CMOS devices

Author

Kampen, C. ; Burenkov, A. ; Lorenz, J. ; Ryssel, H.

Author_Institution

Fraunhofer Inst. of Integrated Syst. & Device Technol. (IISB), Erlangen

fYear

2009

fDate

18-20 March 2009

Firstpage

273

Lastpage

276

Abstract

The simulation of process options for advanced CMOS devices is discussed in this work. Advanced rapid thermal annealing schemes are applied to fully depleted silicon on insulator MOSFETs with a physical gate length of 22 nm. Process induced mechanical stress is simulated for PMOS transistors to improve the I_on-I_off relation. A modification of the linear piezo model is presented to simulate the hole mobility enhancement by mechanical stress. Contact resistances are reduced by using shallow contact trenches. Finally, the dynamic behavior is improved by replacing nitride spacers by oxide spacers.

Keywords

CMOS integrated circuits; MOSFET; contact resistance; hole mobility; rapid thermal annealing; semiconductor process modelling; silicon-on-insulator; CMOS devices; PMOS transistors; contact resistance; contact trenches; fully depleted silicon on insulator MOSFET; gate length; hole mobility; linear piezo model; process induced mechanical stress; rapid thermal annealing; size 22 nm; CMOS process; CMOS technology; MOS devices; MOSFETs; Rapid thermal annealing; Rapid thermal processing; Semiconductor device modeling; Silicon on insulator technology; Stress; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Ultimate Integration of Silicon, 2009. ULIS 2009. 10th International Conference on

Conference_Location

Aachen

Print_ISBN

978-1-4244-3704-7

Type

conf

DOI

10.1109/ULIS.2009.4897589

Filename

4897589