Implementation of pipelined LMS adaptive filter for low-power VLSI applications

Author

Dukel, Bulent ; Rizkalla, Maher E. ; Salama, Paul

Author_Institution

Dept. of Electr. & Comput. Eng., Indiana Univ., Indianapolis, IN, USA

Volume

2

fYear

2002

fDate

4-7 Aug. 2002

Abstract

In this paper, we described the implementation of a pipelined low-power 6 taps adaptive filter, based on the least-mean square (LMS) algorithm. The process of the power characterization procedure is very efficient and can be easily set in synthesis based design flows without too much additional effort. The architecture shows a novel tradeoff between algorithmic performance and power dissipation. In this work, we also characterized the power with a natural top-down design methodology with iterative improvement.

Keywords

adaptive filters; circuit optimisation; circuit simulation; integrated circuit design; least mean squares methods; logic design; logic simulation; low-power electronics; parallel processing; pipeline processing; algorithmic performance/power dissipation tradeoff; least-mean square algorithm; low power optimization; low-power VLSI; parallel processing; pipelined LMS adaptive filter; pipelining; power characterization; power consumption; power minimization; relaxed look-ahead; Adaptive filters; Application software; Capacitance; Circuits; Clocks; Energy consumption; Least squares approximation; Pipeline processing; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on

Print_ISBN

0-7803-7523-8

Type

conf

DOI

10.1109/MWSCAS.2002.1186916

Filename

1186916