Fabrication of gated silicon spike emitter structures using micromachining mold technology

Author

Fleming, J.G. ; King, Donald B. ; Barren, C.C.

Author_Institution

Sandia Nat. Labs., Albuquerque, NM, USA

fYear

1996

fDate

7-12 Jul 1996

Firstpage

371

Lastpage

374

Abstract

In order to reduce capacitance between emitter and gate electrodes, it is desirable to maximize the thickness of the oxide separating the electrodes. Parts with large (15 μ) emitter-to-gate electrode spacing have been fabricated using mold micromachining processes. The gates are self aligned to the emitter tip using CMP. The process results in planar features which are potentially compatible with CMOS processing

Keywords

capacitance; elemental semiconductors; micromachining; polishing; silicon; vacuum microelectronics; 15 micron; CMOS processing; CMP; Si; capacitance; emitter-to-gate electrode spacing; field emitter arrays; gated spike emitter structures; micromachining mold technology; planar features; self alignment; CMOS process; Capacitance; Electrodes; Fabrication; Laboratories; Micromachining; Oxidation; Radio frequency; Silicon compounds; Sputter etching;

fLanguage

English

Publisher

ieee

Conference_Titel

Vacuum Microelectronics Conference, 1996. IVMC'96., 9th International

Conference_Location

St. Petersburg

Print_ISBN

0-7803-3594-5

Type

conf

DOI

10.1109/IVMC.1996.601844

Filename

601844

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3293261