Title :
300mm Time Constrained Queue Loop Management
Author :
Van Sickle, David L. ; Hertzler, Erik F.
Author_Institution :
Intel, Chandler
Abstract :
Prior process technology experience identified several segments in 300 mm process flows as cycle-time sensitive. The time between a wafer leaving an operation and being processed at a subsequent operation must be managed or else process defects may occur. These time constrained steps are referred to as "queue loops" because wafers are held in queue until there is high confidence they can be processed within the predetermined timeframe. The problem resides in synchronizing production capacity within each loop while balancing factory favorable cycle-time and cost effective toolset capacity. This paper will discuss the simulation modeling methodology that was utilized to analyze the trade-offs between output and quality-induced operational controls under varying wafer start levels.
Keywords :
computer integrated manufacturing; semiconductor process modelling; wafer bonding; factory cycle-time; operational control; production capacity ynchronisation; semiconductor process modelling; size 300 mm; time constrained queue loop management; toolset capacity; wafer bonding; Analytical models; Costs; Degradation; Engines; Manufacturing processes; Production facilities; Semiconductor device modeling; Technology management; Throughput; Time factors;
Conference_Titel :
Semiconductor Manufacturing, 2006. ISSM 2006. IEEE International Symposium on
Conference_Location :
Tokyo
Print_ISBN :
978-4-9904138-0-4
DOI :
10.1109/ISSM.2006.4493022